// ******************************************************************************
// Copyright     :  Copyright (C) 2021, Hisilicon Technologies Co. Ltd.
// File name     :  mpu_harden_c_union_define.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2021/06/26
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V5.1
// History       :  xxx 2021/06/26 17:53:27 Create file
// ******************************************************************************

#ifndef MPU_HARDEN_C_UNION_DEFINE_H
#define MPU_HARDEN_C_UNION_DEFINE_H

/* Define the union csr_crg_cfg_mpu_harden_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dp_clk_en_mpu_harden : 1;                  /* [0] */
        u32 itf_clk_en_mpu_harden : 1;                 /* [1] */
        u32 sys_ncsi_clk_en_mpu_harden : 1;            /* [2] */
        u32 sys_pie_clk_en_mpu_harden : 1;             /* [3] */
        u32 sys_spi_clk_en_mpu_harden : 1;             /* [4] */
        u32 ncsi_clk_en_mpu_harden : 1;                /* [5] */
        u32 cp_clk_en_mpu_harden : 1;                  /* [6] */
        u32 ncsi_mac_clk_en_mpu_harden : 1;            /* [7] */
        u32 hiss_sc_icg_en_emu_mpu_harden : 1;         /* [8] */
        u32 dp_rst_req_mpu_harden : 1;                 /* [9] */
        u32 itf_rst_req_mpu_harden : 1;                /* [10] */
        u32 sys_ncsi_rst_req_mpu_harden : 1;           /* [11] */
        u32 sys_pie_rst_req_mpu_harden : 1;            /* [12] */
        u32 sys_spi_rst_req_mpu_harden : 1;            /* [13] */
        u32 spi_rst_req_mpu_harden : 1;                /* [14] */
        u32 ncsi_rst_req_mpu_harden : 1;               /* [15] */
        u32 cp_rst_req_mpu_harden : 1;                 /* [16] */
        u32 ncsi_mac_rst_req_mpu_harden : 1;           /* [17] */
        u32 srst_req_nace_mpu_harden : 1;              /* [18] */
        u32 hiss_sc_srst_req_emu_mpu_harden : 1;       /* [19] */
        u32 hiss_sc_srst_req_emu_power_mpu_harden : 1; /* [20] */
        u32 hiss_sc_srst_req_status_mpu_harden : 1;    /* [21] */
        u32 mpu_sys_clk_sel_mpu_harden : 1;            /* [22] */
        u32 mpu_ncsi_mac_clk_sel_mpu_harden : 1;       /* [23] */
        u32 a5x_clk_sel_mpu_harden : 1;                /* [24] */
        u32 clkoff_gic_mpu_harden : 1;                 /* [25] */
        u32 rsv_0 : 6;                                 /* [31:26] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_crg_cfg_mpu_harden_0_u;

/* Define the union csr_crg_cfg_mpu_harden_1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 icg_en_i2c : 5;    /* [4:0] */
        u32 icg_en_smb : 1;    /* [5] */
        u32 icg_en_uart : 1;   /* [6] */
        u32 icg_en_mdio : 5;   /* [11:7] */
        u32 icg_en_gpio : 4;   /* [15:12] */
        u32 icg_en_ssi : 1;    /* [16] */
        u32 icg_en_ckd : 2;    /* [18:17] */
        u32 srst_req_ckd : 2;  /* [20:19] */
        u32 srst_req_i2c : 5;  /* [25:21] */
        u32 srst_req_smb : 1;  /* [26] */
        u32 srst_req_uart : 1; /* [27] */
        u32 icg_en_wdg : 1;    /* [28] */
        u32 rsv_1 : 3;         /* [31:29] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_crg_cfg_mpu_harden_1_u;

/* Define the union csr_crg_cfg_mpu_harden_2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 srst_req_gpio : 4;       /* [3:0] */
        u32 srst_req_ssi : 1;        /* [4] */
        u32 srst_req_dbg_i2c : 1;    /* [5] */
        u32 srst_req_mpu_apb : 1;    /* [6] */
        u32 srst_req_cp_ring : 1;    /* [7] */
        u32 srst_req_mdio : 5;       /* [12:8] */
        u32 up_peri_sys_clk_sel : 1; /* [13] */
        u32 sc_all_scan_disable : 1; /* [14] */
        u32 srst_req_hva_cpi : 1;    /* [15] */
        u32 srst_req_its : 1;        /* [16] */
        u32 srst_req_mbigen : 1;     /* [17] */
        u32 srst_req_djtag : 1;      /* [18] */
        u32 srst_req_dcip : 1;       /* [19] */
        u32 icg_en_hiss_axi : 1;     /* [20] */
        u32 icg_en_hiss_apb : 1;     /* [21] */
        u32 icg_en_hiss_ahb : 1;     /* [22] */
        u32 icg_en_hva_cpi : 1;      /* [23] */
        u32 icg_en_its : 1;          /* [24] */
        u32 icg_en_mbigen : 1;       /* [25] */
        u32 icg_en_smmu : 1;         /* [26] */
        u32 icg_en_smmu_trans : 1;   /* [27] */
        u32 icg_en_djtag : 1;        /* [28] */
        u32 icg_en_dcip : 1;         /* [29] */
        u32 djtag_clk_sel : 1;       /* [30] */
        u32 rsv_2 : 1;               /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_crg_cfg_mpu_harden_2_u;

/* Define the union csr_crg_cfg_pcie_rc_harden_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 icg_en_smmu_pcie_rc_harden : 1;          /* [0] */
        u32 icg_en_smmu_trans_pcie_rc_harden : 1;    /* [1] */
        u32 icg_en_mclk_pcie_rc_harden : 2;          /* [3:2] */
        u32 icg_en_rxoclk_pcie_rc_harden : 4;        /* [7:4] */
        u32 icg_en_sds4_pma_tx_pcie_rc_harden : 1;   /* [8] */
        u32 icg_en_sds4_pma_rx_pcie_rc_harden : 2;   /* [10:9] */
        u32 icg_en_sds5_pma_tx_pcie_rc_harden : 1;   /* [11] */
        u32 icg_en_sds5_pma_rx_pcie_rc_harden : 2;   /* [13:12] */
        u32 icg_en_pipe_pcie_rc_harden : 4;          /* [17:14] */
        u32 icg_en_hipciec_tl_dl_pcie_rc_harden : 2; /* [19:18] */
        u32 icg_en_pcs_rx_pcie_rc_harden : 4;        /* [23:20] */
        u32 icg_en_pcs_tx_pcie_rc_harden : 4;        /* [27:24] */
        u32 icg_en_pcs_local_pcie_rc_harden : 1;     /* [28] */
        u32 icg_en_apb_pcie_rc_harden : 1;           /* [29] */
        u32 icg_en_axi_pcie_rc_harden : 1;           /* [30] */
        u32 rsv_3 : 1;                               /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_crg_cfg_pcie_rc_harden_0_u;

/* Define the union csr_crg_cfg_pcie_rc_harden_1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 srst_req_sds4_pma_tx_pcie_rc_harden : 1;   /* [0] */
        u32 srst_req_sds4_pma_rx_pcie_rc_harden : 2;   /* [2:1] */
        u32 srst_req_sds5_pma_tx_pcie_rc_harden : 1;   /* [3] */
        u32 srst_req_sds5_pma_rx_pcie_rc_harden : 2;   /* [5:4] */
        u32 srst_req_cfg_bus_pcie_rc_harden : 1;       /* [6] */
        u32 pcie_rc_sys_clk_sel_pcie_rc_harden : 1;    /* [7] */
        u32 soft_rst_req_pcie_port_pcie_rc_harden : 2; /* [9:8] */
        u32 soft_rst_req_pcie_axi_pcie_rc_harden : 1;  /* [10] */
        u32 soft_rst_req_pcie_apb_pcie_rc_harden : 1;  /* [11] */
        u32 soft_rst_req_pcie_pcie_rc_harden : 1;      /* [12] */
        u32 srst_ras_req_pcie_rc_harden : 1;           /* [13] */
        u32 func_mbist_clk_sel_pcie_rc_harden : 1;     /* [14] */
        u32 icg_en_probe_pcie_rc_harden : 1;           /* [15] */
        u32 sds_rc_mclk_icg_en_sel_pcie_rc_harden : 2; /* [17:16] */
        u32 rsv_4 : 14;                                /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_crg_cfg_pcie_rc_harden_1_u;

/* Define the union csr_pcie_rc_power_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcie_rc_pwr_on : 1; /* [0] */
        u32 pcie_rc_iso_en : 1; /* [1] */
        u32 rsv_5 : 30;         /* [31:2] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie_rc_power_cfg_u;

/* Define the union csr_pcie_rc_power_ack_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcie_rc_pwr_ack : 1; /* [0] */
        u32 rsv_6 : 31;          /* [31:1] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie_rc_power_ack_u;

/* Define the union csr_crg_cfg_lcam_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 icg_en_lcam_cp_lcam_harden : 1;       /* [0] */
        u32 icg_en_lcam_lcam_harden : 5;          /* [5:1] */
        u32 icg_en_lcam_common_lcam_harden : 1;   /* [6] */
        u32 icg_en_ring_lcam_harden : 1;          /* [7] */
        u32 srst_req_lcam_cp_lcam_harden : 1;     /* [8] */
        u32 srst_req_lcam_lcam_harden : 5;        /* [13:9] */
        u32 srst_req_lcam_common_lcam_harden : 1; /* [14] */
        u32 srst_req_ring_lcam_harden : 1;        /* [15] */
        u32 lcam_clk_div_sel : 2;                 /* [17:16] */
        u32 rsv_7 : 14;                           /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_crg_cfg_lcam_harden_u;

/* Define the union csr_ring_sta_mpu_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rs_nd_pe_crdt_sta_mpu_harden : 10; /* [9:0] */
        u32 rsv_8 : 22;                        /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_ring_sta_mpu_harden_u;

/* Define the union csr_ring_sta_lcam_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rs_nd_pe_crdt_sta_lcam_harden : 10; /* [9:0] */
        u32 rsv_9 : 22;                         /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_ring_sta_lcam_harden_u;

/* Define the union csr_dcip_cfg_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 detect_enable : 3; /* [2:0] */
        u32 clk_div_cfg : 2;   /* [4:3] */
        u32 detect_period : 2; /* [6:5] */
        u32 dff_ignore : 14;   /* [20:7] */
        u32 rsv_10 : 11;       /* [31:21] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_dcip_cfg_0_u;

/* Define the union csr_dcip_cfg_1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dff_limit : 14;       /* [13:0] */
        u32 dff_test_e : 1;       /* [14] */
        u32 dff_tsel : 3;         /* [17:15] */
        u32 dc_tsel : 2;          /* [19:18] */
        u32 bypass_enable : 1;    /* [20] */
        u32 force_err_enable : 1; /* [21] */
        u32 test_in : 8;          /* [29:22] */
        u32 rsv_11 : 2;           /* [31:30] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_dcip_cfg_1_u;

/* Define the union csr_dcip_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 inner_flag : 1;     /* [0] */
        u32 inner_flag_now : 1; /* [1] */
        u32 outer_flag : 1;     /* [2] */
        u32 outer_flag_now : 1; /* [3] */
        u32 mid_flag : 1;       /* [4] */
        u32 mid_flag_now : 1;   /* [5] */
        u32 dff_location : 14;  /* [19:6] */
        u32 dff_state : 2;      /* [21:20] */
        u32 test_out : 8;       /* [29:22] */
        u32 rsv_12 : 2;         /* [31:30] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_dcip_status_u;

/* Define the union csr_pad_in_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 test_mode0 : 1;       /* [0] */
        u32 test_mode1 : 1;       /* [1] */
        u32 test_mode2 : 1;       /* [2] */
        u32 boot_sel0 : 1;        /* [3] */
        u32 boot_sel1 : 1;        /* [4] */
        u32 i2c_slv_addr0 : 1;    /* [5] */
        u32 i2c_slv_addr1 : 1;    /* [6] */
        u32 boot_mode : 1;        /* [7] */
        u32 ncsi_nc_package0 : 1; /* [8] */
        u32 ncsi_nc_package1 : 1; /* [9] */
        u32 ncsi_nc_package2 : 1; /* [10] */
        u32 rsv_13 : 21;          /* [31:11] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pad_in_status_u;

/* Define the union csr_dft_mpu_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 funcmbist_reset_n : 1; /* [0] */
        u32 rsv_14 : 31;           /* [31:1] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_dft_mpu_u;

/* Define the union csr_hiss_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hiss_sc_corepreq : 1;            /* [0] */
        u32 hiss_sc_corepastate : 1;         /* [1] */
        u32 hiss_dgback_hiss_mask : 1;       /* [2] */
        u32 hiss_sc_enable : 1;              /* [3] */
        u32 hiss_sc_isolate_cpu : 1;         /* [4] */
        u32 hiss_sc_idle_isolate_bypass : 1; /* [5] */
        u32 rsv_15 : 26;                     /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hiss_ctrl_u;

/* Define the union csr_hiss_ctrl_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hiss_sc_corepaccept : 1;   /* [0] */
        u32 hiss_sc_corepactive : 2;   /* [2:1] */
        u32 hiss_sc_corepdeny : 1;     /* [3] */
        u32 hiss_sc_core_idle : 1;     /* [4] */
        u32 hiss_sc_corepowerdown : 1; /* [5] */
        u32 hiss_sc_debug_info : 7;    /* [12:6] */
        u32 rsv_16 : 19;               /* [31:13] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hiss_ctrl_status_u;

/* Define the union csr_tile_jtag_en_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 tile_jtag_en : 8; /* [7:0] */
        u32 rsv_17 : 24;      /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_tile_jtag_en_u;

/* Define the union csr_cfg_mpu_cpl_icl_mem_ctrl_bus_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_mpu_mem_ctrl_0 : 13; /* [12:0] */
        u32 cfg_mpu_mem_ctrl_1 : 15; /* [27:13] */
        u32 rsv_18 : 4;              /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_cfg_mpu_cpl_icl_mem_ctrl_bus_0_u;

/* Define the union csr_cfg_mpu_cpl_icl_mem_ctrl_bus_1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_mpu_mem_ctrl_2 : 13; /* [12:0] */
        u32 cfg_mpu_mem_ctrl_3 : 13; /* [25:13] */
        u32 rsv_19 : 6;              /* [31:26] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_cfg_mpu_cpl_icl_mem_ctrl_bus_1_u;

/* Define the union csr_cfg_mpu_cpl_icl_mem_ctrl_bus_2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_mpu_mem_ctrl_4 : 13; /* [12:0] */
        u32 cfg_mpu_mem_ctrl_5 : 13; /* [25:13] */
        u32 rsv_20 : 6;              /* [31:26] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_cfg_mpu_cpl_icl_mem_ctrl_bus_2_u;

/* Define the union csr_cfg_mpu_cpl_icl_mem_ctrl_bus_3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_mpu_mem_ctrl_6 : 15; /* [14:0] */
        u32 cfg_mpu_mem_ctrl_7 : 13; /* [27:15] */
        u32 rsv_21 : 4;              /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_cfg_mpu_cpl_icl_mem_ctrl_bus_3_u;

/* Define the union csr_cfg_mpu_cpl_icl_mem_ctrl_bus_4_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_mpu_mem_ctrl_8 : 13; /* [12:0] */
        u32 cfg_mpu_mem_ctrl_9 : 13; /* [25:13] */
        u32 rsv_22 : 6;              /* [31:26] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_cfg_mpu_cpl_icl_mem_ctrl_bus_4_u;

/* Define the union csr_efuse_die_id_2k_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 efuse_die_id_2k : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_efuse_die_id_2k_u;

/* Define the union csr_efuse_die_id_4k_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 efuse_die_id_4k : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_efuse_die_id_4k_u;

/* Define the union csr_djtag_clk_div_num_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 djtag_clk_div_num : 4; /* [3:0] */
        u32 rsv_23 : 28;           /* [31:4] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_djtag_clk_div_num_u;

/* Define the union csr_icg_en_kisdon_tap_tck_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 icg_en_kisdon_tap_tck : 8; /* [7:0] */
        u32 rsv_24 : 24;               /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_icg_en_kisdon_tap_tck_u;

/* Define the union csr_sfc_dq3_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sfc_dq3_ctrl_en : 1; /* [0] */
        u32 rsv_25 : 31;         /* [31:1] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_sfc_dq3_ctrl_u;

/* Define the union csr_node_apb_pslverr_pad_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 node_apb_pslverr_pad_cfg : 1; /* [0] */
        u32 rsv_26 : 31;                  /* [31:1] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_node_apb_pslverr_pad_cfg_u;

/* Define the union csr_jtag_auth_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sc2ja_selftest_enb : 1;  /* [0] */
        u32 sc2ja_emsa_pss_sel : 1;  /* [1] */
        u32 hi_1280e_die_sel : 1;    /* [2] */
        u32 ja2jalite_auth_res : 1;  /* [3] */
        u32 jtag_auth_result_en : 1; /* [4] */
        u32 rsv_27 : 27;             /* [31:5] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_jtag_auth_ctrl_u;

/* Define the union csr_jtag_auth_result_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 jtag_auth_result : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_jtag_auth_result_u;

/* Define the union csr_jtag_heart_beat_num_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 jtag_heart_beat_num : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_jtag_heart_beat_num_u;

/* Define the union csr_efuse_sw_rst_n_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 efuse_4k_rst : 1; /* [0] */
        u32 efuse_2k_rst : 1; /* [1] */
        u32 rsv_28 : 30;      /* [31:2] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_efuse_sw_rst_n_u;

/* Define the union csr_efuse_repair_done_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 efuse_4k_repair_done : 1;  /* [0] */
        u32 efuse_2k_repair_done : 1;  /* [1] */
        u32 efuse_dft_repair_done : 1; /* [2] */
        u32 efuse_repair_done_all : 1; /* [3] */
        u32 rsv_29 : 28;               /* [31:4] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_efuse_repair_done_u;


// ==============================================================================
/* Define the global struct */
typedef struct {
    volatile csr_crg_cfg_mpu_harden_0_u crg_cfg_mpu_harden_0;                     /* 0 */
    volatile csr_crg_cfg_mpu_harden_1_u crg_cfg_mpu_harden_1;                     /* 4 */
    volatile csr_crg_cfg_mpu_harden_2_u crg_cfg_mpu_harden_2;                     /* 8 */
    volatile csr_crg_cfg_pcie_rc_harden_0_u crg_cfg_pcie_rc_harden_0;             /* C */
    volatile csr_crg_cfg_pcie_rc_harden_1_u crg_cfg_pcie_rc_harden_1;             /* 10 */
    volatile csr_pcie_rc_power_cfg_u pcie_rc_power_cfg;                           /* 14 */
    volatile csr_pcie_rc_power_ack_u pcie_rc_power_ack;                           /* 18 */
    volatile csr_crg_cfg_lcam_harden_u crg_cfg_lcam_harden;                       /* 1C */
    volatile csr_ring_sta_mpu_harden_u ring_sta_mpu_harden;                       /* 20 */
    volatile csr_ring_sta_lcam_harden_u ring_sta_lcam_harden;                     /* 24 */
    volatile csr_dcip_cfg_0_u dcip_cfg_0;                                         /* 28 */
    volatile csr_dcip_cfg_1_u dcip_cfg_1;                                         /* 2C */
    volatile csr_dcip_status_u dcip_status;                                       /* 30 */
    volatile csr_pad_in_status_u pad_in_status;                                   /* 34 */
    volatile csr_dft_mpu_u dft_mpu;                                               /* 38 */
    volatile csr_hiss_ctrl_u hiss_ctrl;                                           /* 3C */
    volatile csr_hiss_ctrl_status_u hiss_ctrl_status;                             /* 40 */
    volatile csr_tile_jtag_en_u tile_jtag_en;                                     /* 44 */
    volatile csr_cfg_mpu_cpl_icl_mem_ctrl_bus_0_u cfg_mpu_cpl_icl_mem_ctrl_bus_0; /* 48 */
    volatile csr_cfg_mpu_cpl_icl_mem_ctrl_bus_1_u cfg_mpu_cpl_icl_mem_ctrl_bus_1; /* 4C */
    volatile csr_cfg_mpu_cpl_icl_mem_ctrl_bus_2_u cfg_mpu_cpl_icl_mem_ctrl_bus_2; /* 50 */
    volatile csr_cfg_mpu_cpl_icl_mem_ctrl_bus_3_u cfg_mpu_cpl_icl_mem_ctrl_bus_3; /* 54 */
    volatile csr_cfg_mpu_cpl_icl_mem_ctrl_bus_4_u cfg_mpu_cpl_icl_mem_ctrl_bus_4; /* 58 */
    volatile csr_efuse_die_id_2k_u efuse_die_id_2k[64];                           /* 200 */
    volatile csr_efuse_die_id_4k_u efuse_die_id_4k[128];                          /* 300 */
    volatile csr_djtag_clk_div_num_u djtag_clk_div_num;                           /* 500 */
    volatile csr_icg_en_kisdon_tap_tck_u icg_en_kisdon_tap_tck;                   /* 504 */
    volatile csr_sfc_dq3_ctrl_u sfc_dq3_ctrl;                                     /* 508 */
    volatile csr_node_apb_pslverr_pad_cfg_u node_apb_pslverr_pad_cfg;             /* 50C */
    volatile csr_jtag_auth_ctrl_u jtag_auth_ctrl;                                 /* 510 */
    volatile csr_jtag_auth_result_u jtag_auth_result[2];                          /* 514 */
    volatile csr_jtag_heart_beat_num_u jtag_heart_beat_num;                       /* 51C */
    volatile csr_efuse_sw_rst_n_u efuse_sw_rst_n;                                 /* 520 */
    volatile csr_efuse_repair_done_u efuse_repair_done;                           /* 524 */
} S_mpu_harden_node_csr_REGS_TYPE;

/* Declare the struct pointor of the module mpu_harden_node_csr */
extern volatile S_mpu_harden_node_csr_REGS_TYPE *gopmpu_harden_node_csrAllReg;

/* Declare the functions that set the member value */
int iSetCRG_CFG_MPU_HARDEN_0_dp_clk_en_mpu_harden(unsigned int udp_clk_en_mpu_harden);
int iSetCRG_CFG_MPU_HARDEN_0_itf_clk_en_mpu_harden(unsigned int uitf_clk_en_mpu_harden);
int iSetCRG_CFG_MPU_HARDEN_0_sys_ncsi_clk_en_mpu_harden(unsigned int usys_ncsi_clk_en_mpu_harden);
int iSetCRG_CFG_MPU_HARDEN_0_sys_pie_clk_en_mpu_harden(unsigned int usys_pie_clk_en_mpu_harden);
int iSetCRG_CFG_MPU_HARDEN_0_sys_spi_clk_en_mpu_harden(unsigned int usys_spi_clk_en_mpu_harden);
int iSetCRG_CFG_MPU_HARDEN_0_ncsi_clk_en_mpu_harden(unsigned int uncsi_clk_en_mpu_harden);
int iSetCRG_CFG_MPU_HARDEN_0_cp_clk_en_mpu_harden(unsigned int ucp_clk_en_mpu_harden);
int iSetCRG_CFG_MPU_HARDEN_0_ncsi_mac_clk_en_mpu_harden(unsigned int uncsi_mac_clk_en_mpu_harden);
int iSetCRG_CFG_MPU_HARDEN_0_hiss_sc_icg_en_emu_mpu_harden(unsigned int uhiss_sc_icg_en_emu_mpu_harden);
int iSetCRG_CFG_MPU_HARDEN_0_dp_rst_req_mpu_harden(unsigned int udp_rst_req_mpu_harden);
int iSetCRG_CFG_MPU_HARDEN_0_itf_rst_req_mpu_harden(unsigned int uitf_rst_req_mpu_harden);
int iSetCRG_CFG_MPU_HARDEN_0_sys_ncsi_rst_req_mpu_harden(unsigned int usys_ncsi_rst_req_mpu_harden);
int iSetCRG_CFG_MPU_HARDEN_0_sys_pie_rst_req_mpu_harden(unsigned int usys_pie_rst_req_mpu_harden);
int iSetCRG_CFG_MPU_HARDEN_0_sys_spi_rst_req_mpu_harden(unsigned int usys_spi_rst_req_mpu_harden);
int iSetCRG_CFG_MPU_HARDEN_0_spi_rst_req_mpu_harden(unsigned int uspi_rst_req_mpu_harden);
int iSetCRG_CFG_MPU_HARDEN_0_ncsi_rst_req_mpu_harden(unsigned int uncsi_rst_req_mpu_harden);
int iSetCRG_CFG_MPU_HARDEN_0_cp_rst_req_mpu_harden(unsigned int ucp_rst_req_mpu_harden);
int iSetCRG_CFG_MPU_HARDEN_0_ncsi_mac_rst_req_mpu_harden(unsigned int uncsi_mac_rst_req_mpu_harden);
int iSetCRG_CFG_MPU_HARDEN_0_srst_req_nace_mpu_harden(unsigned int usrst_req_nace_mpu_harden);
int iSetCRG_CFG_MPU_HARDEN_0_hiss_sc_srst_req_emu_mpu_harden(unsigned int uhiss_sc_srst_req_emu_mpu_harden);
int iSetCRG_CFG_MPU_HARDEN_0_hiss_sc_srst_req_emu_power_mpu_harden(unsigned int uhiss_sc_srst_req_emu_power_mpu_harden);
int iSetCRG_CFG_MPU_HARDEN_0_hiss_sc_srst_req_status_mpu_harden(unsigned int uhiss_sc_srst_req_status_mpu_harden);
int iSetCRG_CFG_MPU_HARDEN_0_mpu_sys_clk_sel_mpu_harden(unsigned int umpu_sys_clk_sel_mpu_harden);
int iSetCRG_CFG_MPU_HARDEN_0_mpu_ncsi_mac_clk_sel_mpu_harden(unsigned int umpu_ncsi_mac_clk_sel_mpu_harden);
int iSetCRG_CFG_MPU_HARDEN_0_a5x_clk_sel_mpu_harden(unsigned int ua5x_clk_sel_mpu_harden);
int iSetCRG_CFG_MPU_HARDEN_0_clkoff_gic_mpu_harden(unsigned int uclkoff_gic_mpu_harden);
int iSetCRG_CFG_MPU_HARDEN_1_icg_en_i2c(unsigned int uicg_en_i2c);
int iSetCRG_CFG_MPU_HARDEN_1_icg_en_smb(unsigned int uicg_en_smb);
int iSetCRG_CFG_MPU_HARDEN_1_icg_en_uart(unsigned int uicg_en_uart);
int iSetCRG_CFG_MPU_HARDEN_1_icg_en_mdio(unsigned int uicg_en_mdio);
int iSetCRG_CFG_MPU_HARDEN_1_icg_en_gpio(unsigned int uicg_en_gpio);
int iSetCRG_CFG_MPU_HARDEN_1_icg_en_ssi(unsigned int uicg_en_ssi);
int iSetCRG_CFG_MPU_HARDEN_1_icg_en_ckd(unsigned int uicg_en_ckd);
int iSetCRG_CFG_MPU_HARDEN_1_srst_req_ckd(unsigned int usrst_req_ckd);
int iSetCRG_CFG_MPU_HARDEN_1_srst_req_i2c(unsigned int usrst_req_i2c);
int iSetCRG_CFG_MPU_HARDEN_1_srst_req_smb(unsigned int usrst_req_smb);
int iSetCRG_CFG_MPU_HARDEN_1_srst_req_uart(unsigned int usrst_req_uart);
int iSetCRG_CFG_MPU_HARDEN_1_icg_en_wdg(unsigned int uicg_en_wdg);
int iSetCRG_CFG_MPU_HARDEN_2_srst_req_gpio(unsigned int usrst_req_gpio);
int iSetCRG_CFG_MPU_HARDEN_2_srst_req_ssi(unsigned int usrst_req_ssi);
int iSetCRG_CFG_MPU_HARDEN_2_srst_req_dbg_i2c(unsigned int usrst_req_dbg_i2c);
int iSetCRG_CFG_MPU_HARDEN_2_srst_req_mpu_apb(unsigned int usrst_req_mpu_apb);
int iSetCRG_CFG_MPU_HARDEN_2_srst_req_cp_ring(unsigned int usrst_req_cp_ring);
int iSetCRG_CFG_MPU_HARDEN_2_srst_req_mdio(unsigned int usrst_req_mdio);
int iSetCRG_CFG_MPU_HARDEN_2_up_peri_sys_clk_sel(unsigned int uup_peri_sys_clk_sel);
int iSetCRG_CFG_MPU_HARDEN_2_sc_all_scan_disable(unsigned int usc_all_scan_disable);
int iSetCRG_CFG_MPU_HARDEN_2_srst_req_hva_cpi(unsigned int usrst_req_hva_cpi);
int iSetCRG_CFG_MPU_HARDEN_2_srst_req_its(unsigned int usrst_req_its);
int iSetCRG_CFG_MPU_HARDEN_2_srst_req_mbigen(unsigned int usrst_req_mbigen);
int iSetCRG_CFG_MPU_HARDEN_2_srst_req_djtag(unsigned int usrst_req_djtag);
int iSetCRG_CFG_MPU_HARDEN_2_srst_req_dcip(unsigned int usrst_req_dcip);
int iSetCRG_CFG_MPU_HARDEN_2_icg_en_hiss_axi(unsigned int uicg_en_hiss_axi);
int iSetCRG_CFG_MPU_HARDEN_2_icg_en_hiss_apb(unsigned int uicg_en_hiss_apb);
int iSetCRG_CFG_MPU_HARDEN_2_icg_en_hiss_ahb(unsigned int uicg_en_hiss_ahb);
int iSetCRG_CFG_MPU_HARDEN_2_icg_en_hva_cpi(unsigned int uicg_en_hva_cpi);
int iSetCRG_CFG_MPU_HARDEN_2_icg_en_its(unsigned int uicg_en_its);
int iSetCRG_CFG_MPU_HARDEN_2_icg_en_mbigen(unsigned int uicg_en_mbigen);
int iSetCRG_CFG_MPU_HARDEN_2_icg_en_smmu(unsigned int uicg_en_smmu);
int iSetCRG_CFG_MPU_HARDEN_2_icg_en_smmu_trans(unsigned int uicg_en_smmu_trans);
int iSetCRG_CFG_MPU_HARDEN_2_icg_en_djtag(unsigned int uicg_en_djtag);
int iSetCRG_CFG_MPU_HARDEN_2_icg_en_dcip(unsigned int uicg_en_dcip);
int iSetCRG_CFG_MPU_HARDEN_2_djtag_clk_sel(unsigned int udjtag_clk_sel);
int iSetCRG_CFG_PCIE_RC_HARDEN_0_icg_en_smmu_pcie_rc_harden(unsigned int uicg_en_smmu_pcie_rc_harden);
int iSetCRG_CFG_PCIE_RC_HARDEN_0_icg_en_smmu_trans_pcie_rc_harden(unsigned int uicg_en_smmu_trans_pcie_rc_harden);
int iSetCRG_CFG_PCIE_RC_HARDEN_0_icg_en_mclk_pcie_rc_harden(unsigned int uicg_en_mclk_pcie_rc_harden);
int iSetCRG_CFG_PCIE_RC_HARDEN_0_icg_en_rxoclk_pcie_rc_harden(unsigned int uicg_en_rxoclk_pcie_rc_harden);
int iSetCRG_CFG_PCIE_RC_HARDEN_0_icg_en_sds4_pma_tx_pcie_rc_harden(unsigned int uicg_en_sds4_pma_tx_pcie_rc_harden);
int iSetCRG_CFG_PCIE_RC_HARDEN_0_icg_en_sds4_pma_rx_pcie_rc_harden(unsigned int uicg_en_sds4_pma_rx_pcie_rc_harden);
int iSetCRG_CFG_PCIE_RC_HARDEN_0_icg_en_sds5_pma_tx_pcie_rc_harden(unsigned int uicg_en_sds5_pma_tx_pcie_rc_harden);
int iSetCRG_CFG_PCIE_RC_HARDEN_0_icg_en_sds5_pma_rx_pcie_rc_harden(unsigned int uicg_en_sds5_pma_rx_pcie_rc_harden);
int iSetCRG_CFG_PCIE_RC_HARDEN_0_icg_en_pipe_pcie_rc_harden(unsigned int uicg_en_pipe_pcie_rc_harden);
int iSetCRG_CFG_PCIE_RC_HARDEN_0_icg_en_hipciec_tl_dl_pcie_rc_harden(unsigned int uicg_en_hipciec_tl_dl_pcie_rc_harden);
int iSetCRG_CFG_PCIE_RC_HARDEN_0_icg_en_pcs_rx_pcie_rc_harden(unsigned int uicg_en_pcs_rx_pcie_rc_harden);
int iSetCRG_CFG_PCIE_RC_HARDEN_0_icg_en_pcs_tx_pcie_rc_harden(unsigned int uicg_en_pcs_tx_pcie_rc_harden);
int iSetCRG_CFG_PCIE_RC_HARDEN_0_icg_en_pcs_local_pcie_rc_harden(unsigned int uicg_en_pcs_local_pcie_rc_harden);
int iSetCRG_CFG_PCIE_RC_HARDEN_0_icg_en_apb_pcie_rc_harden(unsigned int uicg_en_apb_pcie_rc_harden);
int iSetCRG_CFG_PCIE_RC_HARDEN_0_icg_en_axi_pcie_rc_harden(unsigned int uicg_en_axi_pcie_rc_harden);
int iSetCRG_CFG_PCIE_RC_HARDEN_1_srst_req_sds4_pma_tx_pcie_rc_harden(unsigned int usrst_req_sds4_pma_tx_pcie_rc_harden);
int iSetCRG_CFG_PCIE_RC_HARDEN_1_srst_req_sds4_pma_rx_pcie_rc_harden(unsigned int usrst_req_sds4_pma_rx_pcie_rc_harden);
int iSetCRG_CFG_PCIE_RC_HARDEN_1_srst_req_sds5_pma_tx_pcie_rc_harden(unsigned int usrst_req_sds5_pma_tx_pcie_rc_harden);
int iSetCRG_CFG_PCIE_RC_HARDEN_1_srst_req_sds5_pma_rx_pcie_rc_harden(unsigned int usrst_req_sds5_pma_rx_pcie_rc_harden);
int iSetCRG_CFG_PCIE_RC_HARDEN_1_srst_req_cfg_bus_pcie_rc_harden(unsigned int usrst_req_cfg_bus_pcie_rc_harden);
int iSetCRG_CFG_PCIE_RC_HARDEN_1_pcie_rc_sys_clk_sel_pcie_rc_harden(unsigned int upcie_rc_sys_clk_sel_pcie_rc_harden);
int iSetCRG_CFG_PCIE_RC_HARDEN_1_soft_rst_req_pcie_port_pcie_rc_harden(
    unsigned int usoft_rst_req_pcie_port_pcie_rc_harden);
int iSetCRG_CFG_PCIE_RC_HARDEN_1_soft_rst_req_pcie_axi_pcie_rc_harden(
    unsigned int usoft_rst_req_pcie_axi_pcie_rc_harden);
int iSetCRG_CFG_PCIE_RC_HARDEN_1_soft_rst_req_pcie_apb_pcie_rc_harden(
    unsigned int usoft_rst_req_pcie_apb_pcie_rc_harden);
int iSetCRG_CFG_PCIE_RC_HARDEN_1_soft_rst_req_pcie_pcie_rc_harden(unsigned int usoft_rst_req_pcie_pcie_rc_harden);
int iSetCRG_CFG_PCIE_RC_HARDEN_1_srst_ras_req_pcie_rc_harden(unsigned int usrst_ras_req_pcie_rc_harden);
int iSetCRG_CFG_PCIE_RC_HARDEN_1_func_mbist_clk_sel_pcie_rc_harden(unsigned int ufunc_mbist_clk_sel_pcie_rc_harden);
int iSetCRG_CFG_PCIE_RC_HARDEN_1_icg_en_probe_pcie_rc_harden(unsigned int uicg_en_probe_pcie_rc_harden);
int iSetCRG_CFG_PCIE_RC_HARDEN_1_sds_rc_mclk_icg_en_sel_pcie_rc_harden(
    unsigned int usds_rc_mclk_icg_en_sel_pcie_rc_harden);
int iSetPCIE_RC_POWER_CFG_pcie_rc_pwr_on(unsigned int upcie_rc_pwr_on);
int iSetPCIE_RC_POWER_CFG_pcie_rc_iso_en(unsigned int upcie_rc_iso_en);
int iSetPCIE_RC_POWER_ACK_pcie_rc_pwr_ack(unsigned int upcie_rc_pwr_ack);
int iSetCRG_CFG_LCAM_HARDEN_icg_en_lcam_cp_lcam_harden(unsigned int uicg_en_lcam_cp_lcam_harden);
int iSetCRG_CFG_LCAM_HARDEN_icg_en_lcam_lcam_harden(unsigned int uicg_en_lcam_lcam_harden);
int iSetCRG_CFG_LCAM_HARDEN_icg_en_lcam_common_lcam_harden(unsigned int uicg_en_lcam_common_lcam_harden);
int iSetCRG_CFG_LCAM_HARDEN_icg_en_ring_lcam_harden(unsigned int uicg_en_ring_lcam_harden);
int iSetCRG_CFG_LCAM_HARDEN_srst_req_lcam_cp_lcam_harden(unsigned int usrst_req_lcam_cp_lcam_harden);
int iSetCRG_CFG_LCAM_HARDEN_srst_req_lcam_lcam_harden(unsigned int usrst_req_lcam_lcam_harden);
int iSetCRG_CFG_LCAM_HARDEN_srst_req_lcam_common_lcam_harden(unsigned int usrst_req_lcam_common_lcam_harden);
int iSetCRG_CFG_LCAM_HARDEN_srst_req_ring_lcam_harden(unsigned int usrst_req_ring_lcam_harden);
int iSetCRG_CFG_LCAM_HARDEN_lcam_clk_div_sel(unsigned int ulcam_clk_div_sel);
int iSetRING_STA_MPU_HARDEN_rs_nd_pe_crdt_sta_mpu_harden(unsigned int urs_nd_pe_crdt_sta_mpu_harden);
int iSetRING_STA_LCAM_HARDEN_rs_nd_pe_crdt_sta_lcam_harden(unsigned int urs_nd_pe_crdt_sta_lcam_harden);
int iSetDCIP_CFG_0_detect_enable(unsigned int udetect_enable);
int iSetDCIP_CFG_0_clk_div_cfg(unsigned int uclk_div_cfg);
int iSetDCIP_CFG_0_detect_period(unsigned int udetect_period);
int iSetDCIP_CFG_0_dff_ignore(unsigned int udff_ignore);
int iSetDCIP_CFG_1_dff_limit(unsigned int udff_limit);
int iSetDCIP_CFG_1_dff_test_e(unsigned int udff_test_e);
int iSetDCIP_CFG_1_dff_tsel(unsigned int udff_tsel);
int iSetDCIP_CFG_1_dc_tsel(unsigned int udc_tsel);
int iSetDCIP_CFG_1_bypass_enable(unsigned int ubypass_enable);
int iSetDCIP_CFG_1_force_err_enable(unsigned int uforce_err_enable);
int iSetDCIP_CFG_1_test_in(unsigned int utest_in);
int iSetDCIP_STATUS_inner_flag(unsigned int uinner_flag);
int iSetDCIP_STATUS_inner_flag_now(unsigned int uinner_flag_now);
int iSetDCIP_STATUS_outer_flag(unsigned int uouter_flag);
int iSetDCIP_STATUS_outer_flag_now(unsigned int uouter_flag_now);
int iSetDCIP_STATUS_mid_flag(unsigned int umid_flag);
int iSetDCIP_STATUS_mid_flag_now(unsigned int umid_flag_now);
int iSetDCIP_STATUS_dff_location(unsigned int udff_location);
int iSetDCIP_STATUS_dff_state(unsigned int udff_state);
int iSetDCIP_STATUS_test_out(unsigned int utest_out);
int iSetPAD_IN_STATUS_test_mode0(unsigned int utest_mode0);
int iSetPAD_IN_STATUS_test_mode1(unsigned int utest_mode1);
int iSetPAD_IN_STATUS_test_mode2(unsigned int utest_mode2);
int iSetPAD_IN_STATUS_boot_sel0(unsigned int uboot_sel0);
int iSetPAD_IN_STATUS_boot_sel1(unsigned int uboot_sel1);
int iSetPAD_IN_STATUS_i2c_slv_addr0(unsigned int ui2c_slv_addr0);
int iSetPAD_IN_STATUS_i2c_slv_addr1(unsigned int ui2c_slv_addr1);
int iSetPAD_IN_STATUS_boot_mode(unsigned int uboot_mode);
int iSetPAD_IN_STATUS_ncsi_nc_package0(unsigned int uncsi_nc_package0);
int iSetPAD_IN_STATUS_ncsi_nc_package1(unsigned int uncsi_nc_package1);
int iSetPAD_IN_STATUS_ncsi_nc_package2(unsigned int uncsi_nc_package2);
int iSetDFT_MPU_funcmbist_reset_n(unsigned int ufuncmbist_reset_n);
int iSetHISS_CTRL_hiss_sc_corepreq(unsigned int uhiss_sc_corepreq);
int iSetHISS_CTRL_hiss_sc_corepastate(unsigned int uhiss_sc_corepastate);
int iSetHISS_CTRL_hiss_dgback_hiss_mask(unsigned int uhiss_dgback_hiss_mask);
int iSetHISS_CTRL_hiss_sc_enable(unsigned int uhiss_sc_enable);
int iSetHISS_CTRL_hiss_sc_isolate_cpu(unsigned int uhiss_sc_isolate_cpu);
int iSetHISS_CTRL_hiss_sc_idle_isolate_bypass(unsigned int uhiss_sc_idle_isolate_bypass);
int iSetHISS_CTRL_STATUS_hiss_sc_corepaccept(unsigned int uhiss_sc_corepaccept);
int iSetHISS_CTRL_STATUS_hiss_sc_corepactive(unsigned int uhiss_sc_corepactive);
int iSetHISS_CTRL_STATUS_hiss_sc_corepdeny(unsigned int uhiss_sc_corepdeny);
int iSetHISS_CTRL_STATUS_hiss_sc_core_idle(unsigned int uhiss_sc_core_idle);
int iSetHISS_CTRL_STATUS_hiss_sc_corepowerdown(unsigned int uhiss_sc_corepowerdown);
int iSetHISS_CTRL_STATUS_hiss_sc_debug_info(unsigned int uhiss_sc_debug_info);
int iSetTILE_JTAG_EN_tile_jtag_en(unsigned int utile_jtag_en);
int iSetCFG_MPU_CPL_ICL_MEM_CTRL_BUS_0_cfg_mpu_mem_ctrl_0(unsigned int ucfg_mpu_mem_ctrl_0);
int iSetCFG_MPU_CPL_ICL_MEM_CTRL_BUS_0_cfg_mpu_mem_ctrl_1(unsigned int ucfg_mpu_mem_ctrl_1);
int iSetCFG_MPU_CPL_ICL_MEM_CTRL_BUS_1_cfg_mpu_mem_ctrl_2(unsigned int ucfg_mpu_mem_ctrl_2);
int iSetCFG_MPU_CPL_ICL_MEM_CTRL_BUS_1_cfg_mpu_mem_ctrl_3(unsigned int ucfg_mpu_mem_ctrl_3);
int iSetCFG_MPU_CPL_ICL_MEM_CTRL_BUS_2_cfg_mpu_mem_ctrl_4(unsigned int ucfg_mpu_mem_ctrl_4);
int iSetCFG_MPU_CPL_ICL_MEM_CTRL_BUS_2_cfg_mpu_mem_ctrl_5(unsigned int ucfg_mpu_mem_ctrl_5);
int iSetCFG_MPU_CPL_ICL_MEM_CTRL_BUS_3_cfg_mpu_mem_ctrl_6(unsigned int ucfg_mpu_mem_ctrl_6);
int iSetCFG_MPU_CPL_ICL_MEM_CTRL_BUS_3_cfg_mpu_mem_ctrl_7(unsigned int ucfg_mpu_mem_ctrl_7);
int iSetCFG_MPU_CPL_ICL_MEM_CTRL_BUS_4_cfg_mpu_mem_ctrl_8(unsigned int ucfg_mpu_mem_ctrl_8);
int iSetCFG_MPU_CPL_ICL_MEM_CTRL_BUS_4_cfg_mpu_mem_ctrl_9(unsigned int ucfg_mpu_mem_ctrl_9);
int iSetEFUSE_DIE_ID_2K_efuse_die_id_2k(unsigned int uefuse_die_id_2k);
int iSetEFUSE_DIE_ID_4K_efuse_die_id_4k(unsigned int uefuse_die_id_4k);
int iSetDJTAG_CLK_DIV_NUM_djtag_clk_div_num(unsigned int udjtag_clk_div_num);
int iSetICG_EN_KISDON_TAP_TCK_icg_en_kisdon_tap_tck(unsigned int uicg_en_kisdon_tap_tck);
int iSetSFC_DQ3_CTRL_sfc_dq3_ctrl_en(unsigned int usfc_dq3_ctrl_en);
int iSetNODE_APB_PSLVERR_PAD_CFG_node_apb_pslverr_pad_cfg(unsigned int unode_apb_pslverr_pad_cfg);
int iSetJTAG_AUTH_CTRL_sc2ja_selftest_enb(unsigned int usc2ja_selftest_enb);
int iSetJTAG_AUTH_CTRL_sc2ja_emsa_pss_sel(unsigned int usc2ja_emsa_pss_sel);
int iSetJTAG_AUTH_CTRL_hi_1280e_die_sel(unsigned int uhi_1280e_die_sel);
int iSetJTAG_AUTH_CTRL_ja2jalite_auth_res(unsigned int uja2jalite_auth_res);
int iSetJTAG_AUTH_CTRL_jtag_auth_result_en(unsigned int ujtag_auth_result_en);
int iSetJTAG_AUTH_RESULT_jtag_auth_result(unsigned int ujtag_auth_result);
int iSetJTAG_HEART_BEAT_NUM_jtag_heart_beat_num(unsigned int ujtag_heart_beat_num);
int iSetEFUSE_SW_RST_N_efuse_4k_rst(unsigned int uefuse_4k_rst);
int iSetEFUSE_SW_RST_N_efuse_2k_rst(unsigned int uefuse_2k_rst);
int iSetEFUSE_REPAIR_DONE_efuse_4k_repair_done(unsigned int uefuse_4k_repair_done);
int iSetEFUSE_REPAIR_DONE_efuse_2k_repair_done(unsigned int uefuse_2k_repair_done);
int iSetEFUSE_REPAIR_DONE_efuse_dft_repair_done(unsigned int uefuse_dft_repair_done);
int iSetEFUSE_REPAIR_DONE_efuse_repair_done_all(unsigned int uefuse_repair_done_all);


#endif // __CSR_C_UNION_DEFINE_H__
